[vox-tech] help with a makefile

[Peter Jay Salzman]

hi all,

here is a makefile for one of my simulators:


TARGET = ising2-periodic
TIMESTAMP = `/bin/date +'%Y-%b-%d-%H-%M'`
BACKUPDIR = /usr/local/backup/ising2
WARN = -Wall -W -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations
CFLAGS = -O9 -ansi $(WARN)
LFLAGS = -lm -L. -lpising2
OBJS := $(patsubst %.c, %.o, $(wildcard *.c))


$(TARGET): $(OBJS)
	gcc -o $@ $(OBJS) $(LFLAGS)

main.o: main.c pising2.h fsignal.h
fsignal.o: fsignal.c fsignal.h

.PHONY: clean
clean:
   -rm -rf *.o a.out $(TARGET)

backup:
	make clean
	cd ..; tar -jcv ./$(TARGET) > "$(BACKUPDIR)/$(TARGET)-$(TIMESTAMP).tar.bz2"
	echo "Saved to $(BACKUPDIR)/$(TARGET)-$(TIMESTAMP)."
	echo "$(TARGET)-$(TIMESTAMP)" > .version

i would *like* to put all object files in ./objs.   i'm having a hard
time figuring out how to do this.  i know how to have make look for the
object files when it *links* the target:

vpath %.o ./objs

but that doesn't help during the *compilation* process.   is there a way
to tell make:

   listen, make.  i like your implicit rules.  but when you make an
   object file, i'd really appreciate it if you put it in "./objs"
   rather than "."

so in other words, i KNOW how to do this by hard-coding the paths into
the makefile.  what i'm really looking for is some kind of directive to
modify the implicit rule.

kind of like how when you define $(CFLAGS) you don't need to explicitly
say:

   target: foo.c foo.h
   	gcc $(CFLAGS) -o $@ $<

because make is smart enough to use your $(CFLAGS) even when you use an
implicit rule:

   target: foo.c foo.h      # $(CFLAGS) is used here

i hope i explained this ok!  :)

pete