[vox-tech] makefile question - auto dependencies
Peter Jay Salzman
vox-tech@lists.lugod.org
Fri, 21 Mar 2003 13:23:48 -0800
begin Mike Simons <msimons@moria.simons-clan.com>
> On Fri, Mar 21, 2003 at 10:18:21AM -0800, Peter Jay Salzman wrote:
> > i was playing around with auto-dependencies with makefiles the other
> > day. here's a hello world example of the technique:
> >
>
> > OBJS = $(patsubst %.c, %.o, $(wildcard *.c))
> > SRCS = $(wildcard *.c)
>
> should use SRCS in OBJS list.
aha. yes, thanks!
> > DEPDIR = .deps
> > vpath %.d ${DEPDIR}
>
> I don't use vpath in the sample above... can add if you want.
>
> > into a single line saying that all .o files depend on the corresponding
> > .d file?
>
> I used to use a nasty sed expression to make the .d files, but for
> some reason decided that they were not needed.
>
> The .o's do not depend on the .d.
>
> Both the .d and .o the depend on the .c.
yes again. :) and user supplied .h files as well.
> Here is a current sample of Makefile which I use to build programs
> with, stripped down to only work on C code... below no user servicable
> parts is the stuff that does auto building.
> Rules are written for C++, ProC, LaTeX, etc.
>
> If you only want a single target to make life simplier you can replace
> go,s2,s3 with:
> ===
> ${TARGET}: ${OFILES}
> gcc ${CFLAGS} -o $@ $^ ${LFLAGS}
> ===
>
> If you care to use a special LD variable to id the linker
> stuff ...
>
> ====
> TARGET := go
>
> CC := gcc
> CFLAGS := -g -Wall -W -O9
> CFLAGS := -g -Wall -W
> LFLAGS := -lm
>
> all: ${TARGET}
>
> go: main.o
> gcc ${CFLAGS} -o $@ $^ ${LFLAGS}
> s2: s2.o
> gcc ${CFLAGS} -o $@ $^ ${LFLAGS}
> s3: s3.o
> gcc ${CFLAGS} -o $@ $^ ${LFLAGS}
>
> ################
> # no user servicable parts below here... so don't change below here
> ################
> %.o: %.c
> gcc ${CFLAGS} -c $^
>
> .%.d: %.c
> @gcc -MM ${CFLAGS} -o $@ $^
>
> clean:
> rm -rf *.o
>
> nuke: clean
> rm -rf ${DFILES} $(TARGET)
>
> CFILES := ${wildcard *.c}
> OFILES := ${patsubst %.c,%.o,${CFILES}}
> DFILES := ${patsubst %.c,.%.d,${CFILES}}
>
> ifneq ($(MAKECMDGOALS),nuke)
> -include ${DFILES}
> endif
hi mike,
i figured you'd answer. ;)
if i'm not mistaken, you're ignoring the dependencies of the .d files on
the .c and .h files. in other words, your .d file will look like:
main.o : main.c main.h
when it should look like:
main.o main.d : main.c main.h
that's what the awful sed script does (i think).
also, is the .o->.c explicit rule really necessary? make already knows
how to make .o files from .c files.
pete
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