[vox-tech] makefile question - auto dependencies

[Peter Jay Salzman]

i was playing around with auto-dependencies with makefiles the other
day.  here's a hello world example of the technique:


   TARGET = hello_world
   CFLAGS = -W -Wall -g
   OBJS   = $(patsubst %.c, %.o, $(wildcard *.c))
   SRCS   = $(wildcard *.c)
   LDLIBS = -lm
   DEPDIR = .deps
   vpath %.d ${DEPDIR}
   
   # Dependencies
   #
   all:           ${TARGET}
   ${TARGET}:     ${OBJS}
   hello_world.o: hello_world.d
   functions.o:   functions.d
   
   # Explicit rules
   #
   %.d: %.c
      @$(CC) -MM $(CPPFLAGS) $< > ${DEPDIR}/$@.$$$$; \
      sed 's,\($*\)\.o[ :]*,\1.o $@ : ,g' < ${DEPDIR}/$@.$$$$ >
   ${DEPDIR}/$@; \
      rm -f ${DEPDIR}/$@.$$$$


sometimes i like seeing how space-efficient i can make things.  this
makefile works really well, but i'm wondering if it can be shortened.
is there a way of specifying the following:

   "the dependency of X.o is X.d where X is any file name"

so in other words, is there a way of combining the three lines:

   hello_world.o: hello_world.d
   functions.o:   functions.d
   utility.o:     utility.d

into a single line saying that all .o files depend on the corresponding
.d file?

thanks,
pete

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